ECE521 : Digital ASIC Design
ECE Cross-Listing : | ECE421: Digital ASIC Design (undergraduate) | |
Semesters : | Spring 2020 | |
Lecture : | HU 0041 , M 17:45 - 20:35 | |
Lab : | HU 0041 , M 17:45 - 20:35 | |
Prerequisites : | Introduction to VLSI. | |
Environment : | Linux, Cadence VLSI ASIC design, synthesis, and analysis tools | |
Description : |
Introduction to Cadence Systems CMOS ASIC development tools. ASIC Synthesis process is introduced using Cadence tool suite. Design Rule Checking (DRC) , Layout Versus Schematic (LVS), and the layout of the power and clock distribution networks of a complex synchronous CMOS VLSI circuit is introduced.
Different phases of the ASIC design cycle are studied: * Verilog description * functional simulation and verification * timing and power analysis * tapeout (GDS layout creation). Students are required to design an ASIC which is fabricated by MOSIS. |
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Workload : | Five individual and two group projects. Projects increase in complexity, with the final project being the most sophisticated. Example final project is a simple RISC microprocessor (e.g., R2000) or a co-processor. | |
Textbook : | Digital VLSI Chip Design with Cadence and Synopsys CAD Tools. Erik Brunvand, ISBN # 978-0321547996. | |