ECE448 (GMU)

ECE 448 : FPGA Design with VHDL



Years :   2021-
Lecture :   IN 132 ,  TTh   10:30 - 11:45 
Lab :   ENGR 3208 , multiple sections
Prerequisites :   ECE445.
Environment :   Digilent Basys3 board. VGA monitor, Windows 10 Pro, Vivado 2021.2 Suite, Vitis 2021.2 Suite.
Description :  

Practical introduction to modeling of digital systems with VHDL for logic synthesis. Overview of design flow and tools for FPGAs. Discusses verification of digital systems using testbenches, prototyping boards and modern testing equipment, and illustrates VHDL-based design methodology with multiple examples from communications, control, DSP, and cryptography. Laboratory experiments create link between simulation and actual hardware implementation based on FPGA boards. Offered by Electrical and Computer Engineering. Limited to two attempts..

Workload :   5 projects, 10 labs, 2 exams.