ECE 262/462 : Advanced CMOS VLSI Design
| Years : | 2009-2016 | |
| Lecture : | CSB 523 , W 15:25 - 16:40 | |
| Lab : | CSB 527 , M 15:25 - 16:40 | |
| Prerequisites : | ECE 261/461 | |
| Environment : | Linux, Cadence VLSI ASIC design, synthesis, and analysis tools | |
| Description : |
Introduction to Cadence Systems CMOS ASIC development tools. ASIC Synthesis process is introduced using Cadence tool suite. Design Rule Checking (DRC) , Layout Versus Schematic (LVS), and the layout of the power and clock distribution networks of a complex synchronous CMOS VLSI circuit is introduced.
Different phases of the ASIC design cycle are studied: * Verilog description * functional simulation and verification * timing and power analysis * tapeout (GDS layout creation). Students are required to design an ASIC which is fabricated by MOSIS. |
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| Workload : | Five individual and two group projects. Projects increase in complexity, with the final project being the most sophisticated. Example final project is a simple RISC microprocessor (e.g., R2000) or a co-processor. |